One of the challenges in designing an image sensor is the need for the image sensor to exhibit a high dynamic range. Many applications, particularly outdoor applications, require the image sensor to have a high dynamic range to account for very bright and very dark areas. For example, some applications may have lighting conditions from below 1 lux for night vision to over 10,000 lux for bright sunlight. Real world scenes may have illumination intensities varying over a 100 dB range or more. While biological vision systems and silver halide film can image high dynamic range (100+ dB) scenes with little loss of contrast information, it has been challenging to develop electronic image sensors to do the same.
Most current image sensors have limited dynamic ranges, typically between 50 dB to 80 dB. Because of this, relevant information content is lost of the captured scene. Thus, it is desirable to have high dynamic range (HDR) image sensor that can more accurately capture the scene.
The large variation of illumination intensity manifests itself in image blooming when these prior art sensors are used to capture a scene with a very bright area. The pixels illuminated by the very bright light source saturate and flood signal onto adjacent pixels so that the bright areas of the output image grow and the true image is lost.
Prior art attempts to increase dynamic range for CMOS image sensors include:                1. Measurement of the number of clock periods to reach a threshold. See, e.g., U.S. Pat. No. 5,650,643 to Konuma.        2. Capture of two or more correlated images with different integration times and then combining the multiple images into a single high dynamic range image. See, e.g., Orly Yadid-Pecht et al. “Wide Intrascene Dynamic Range CMOS APS Using Dual Sampling”, 1997 IEEE Workshop on Charge-Coupled Device and Advanced Image Sensors and D.X.D. Yang et al. “A 640×512 CMOS Image Sensor with Ultra Wide Dynamic Range Floating Point Pixel Level ADC,” ISSCC Digest of Technical Papers, February 1999.        3. Logarithmic transfer function pixel architectures. See, e.g., S. Kavadias et al. “A logarithmic response CMOS image sensor with on-chip calibration”, IEEE J. Solid State Circuits, Vol. 35, No. 8, August 2000.        4. Varying the level of the reset gate during integration. The current to charge transfer function is compressed resulting in higher maximum non-saturation current. See, e.g., U.S. Pat. No. 5.055,667 to Sayag and S. J. Decker et al. “A 256×256 CMOS Imaging Array with Wide Dynamic Range Pixels and Column-Parallel Digital Output”, IEEE J. Solid State Circuits, Vol. 33, pp. 2081-2091, December 1998.        5. Spatially varying the exposure:                    a. An array of neutral density filters is deposited on the sensor so that pixels with darker filters sample high intensity light while pixels with lighter filters sample low intensity light. High dynamic range image is synthesized using low pass filtering or more sophisticated techniques such as cubic interpolation. See e.g., U.S. Pat. No. 6,864,916 to Nayer.            b. Individually resetting the pixels. See, e.g., U.S. Pat. No. 5,892,541 to Merrill and U.S. Pat. No. 6,175,383 to Orly Yadid-Pecht et al.                        
The '383 patent merits additional discussion. As seen in FIG. 1 (a reproduction of FIG. 3 of the '383 patent), the '383 patent implements individual pixel reset with one additional transistor compared to a conventional 3T APS design. The pixels can be reset at different times, but sampling is accomplished at the sample time for all pixels. The time (integration period) between reset time and sample time will vary as desired for each pixel by varying the reset time for each pixel.
As seen in FIG. 1, the '383 patent also teaches non-destructive readout by activating the row select transistor 56 and reading the voltage on the column bus 60. Nondestructive readout can be used to determine the optimum exposure period for a given region of interest.
In operation, when both the row reset line RRST and the column reset line CRST 52 are simultaneously high, the logic reset transistor 48 will turn on and node LRST 50 will be high and the pixel will be reset. Otherwise, the row reset transistor 48 passes a low voltage which does not activate the logical reset transistor. Column reset line 52 is shared with pixels in the same column. Turning to FIG. 2 (a reproduction of FIG. 5 of the '383 patent), the '383 patent shows that by varying the reset time of individual pixels, integration times of T, T1, T2, or T3 can be implemented. Note that each pixel does not include memory and reset times for the pixels must be determined by peripheral processing circuitry.
While this prior art approach is advantageous over other techniques, it still does not provide completely satisfactory performance.